Papers

  1. D. Schall, A. Sandberg, and B. Grot, “Warming Up a Cold Front-End with Ignite,” in Proc. Annual International Symposium on Microarchitecture (MICRO), Oct. 2023. doi: 10.1145/3613424.3614258. To appear. PDF
  2. R. Avanzi, I. Mihalcea, D. Schall, H. Montaner, and A. Sandberg, “Cryptographic Protection of Random Access Memory: How Inconspicuous can Hardening Against the most Powerful Adversaries be?,” Cryptology ePrint Archive, Oct. 2022. Link PDF
  3. D. Schall, A. Margaritov, D. Ustiugov, A. Sandberg, and B. Grot, “Lukewarm Serverless Functions: Characterization and Optimization,” in Proc. International Symposium on Computer Architecture (ISCA), Jun. 2022. doi: 10.1145/3470496.3527390. PDF
  4. C. H. Park, I. Vougioukas, A. Sandberg, and D. Black-Schaffer, “Every Walk’s a Hit: Making Page Walks Single-Access Cache Hits,” in Proc. Internationla Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Feb. 2022, pp. 128–141. doi: 10.1145/3503222.3507718. PDF
  5. I. Vougioukas, A. Sandberg, and N. Nikoleris, “Branch Predicting with Sparse Distributed Memories,” arXiv preprint, Oct. 2021. doi: 10.48550/arXiv.2110.09166.
  6. J. Lowe-Power et al., “The gem5 Simulator: Version 20.0+,” arXiv preprint, Jul. 2020. doi: 10.48550/arXiv.2007.03152.
  7. I. Vougioukas, N. Nikoleris, A. Sandberg, S. Diestelhorst, B. M. Al-Hashimi, and G. V. Merrett, “BRB: Mitigating Branch Predictor Side-Channels,” in Proc. International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2019, pp. 466–477. doi: 10.1109/HPCA.2019.00058.
  8. I. Vougioukas, A. Sandberg, S. Diestelhorst, B. M. Al-Hashimi, and G. V. Merrett, “Nucleus: Finding the Sharing Limit of Heterogeneous Cores,” ACM Transactions on Embedded Computing Systems (TECS), vol. 16, no. 5s, Sep. 2017. doi: 10.1145/3126544.
  9. N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson, “CoolSim: Statistical Techniques to Replace Cache Warming with Efficient, Virtualized Profiling,” in Proc. Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS), Jul. 2016, pp. 106–115. doi: 10.1109/SAMOS.2016.7818337.
  10. R. de Jong and A. Sandberg, “NoMali: Simulating a Realistic Graphics Driver Stack Using a Stub GPU,” in Proc. International Symposium on Performance Analysis of Systems & Software (ISPASS), Apr. 2016, pp. 255–262. doi: 10.1109/ISPASS.2016.7482100.
  11. N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson, “CoolSim: Eliminating Traditional Cache Warming with Fast, Virtualized Profiling,” in Proc. International Symposium on Performance Analysis of Systems & Software (ISPASS), Apr. 2016, pp. 149–150. doi: 10.1109/ISPASS.2016.7482085.
  12. A. Sandberg, N. Nikoleris, T. E. Carlson, E. Hagersten, S. Kaxiras, and D. Black-Schaffer, “Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed,” in Proc. International Symposium on Workload Characterization (IISWC), Oct. 2015, pp. 183–192. doi: 10.1109/IISWC.2015.29.
  13. M. Khan, A. Sandberg, and E. Hagersten, “A Case for Resource Efficient Prefetching in Multicores,” in Proc. International Conference on Parallel Processing (ICPP), Sep. 2014, pp. 101–110. doi: 10.1109/ICPP.2014.19.
  14. A. Sandberg, “Understanding Multicore Performance: Efficient Memory System Modeling and Simulation,” PhD thesis, Uppsala University, 2014. Link PDF
  15. M. Khan, A. Sandberg, and E. Hagersten, “A Case for Resource Efficient Prefetching in Multicores,” Proc. International Symposium on Performance Analysis of Systems & Software (ISPASS). Extended Abstract / Poster, pp. 137–138, Mar. 2014. doi: 10.1109/ISPASS.2014.6844473.
  16. A. Sandberg, E. Hagersten, and D. Black-Schaffer, “Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed,” Department of Information Technology, Uppsala University, 2014-005, Mar. 2014. Link PDF
  17. S. Bischoff et al., “Flexible and High-Speed System-Level Performance Analysis using Hardware-Accelerated Simulation,” Proc. Design, Automation & Test in Europe (DATE). Extended Abstract, Mar. 2013. Link PDF
  18. A. Sandberg, A. Sembrant, D. Black-Schaffer, and E. Hagersten, “Modeling Performance Variation Due to Cache Sharing,” in Proc. International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2013, pp. 155–166. doi: 10.1109/HPCA.2013.6522315. PDF
  19. A. Sandberg, D. Black-Schaffer, and E. Hagersten, “Efficient Techniques for Predicting Cache Sharing and Throughput,” in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2012, pp. 305–314. doi: 10.1145/2370816.2370861. PDF
  20. A. Sandberg, D. Black-Schaffer, and E. Hagersten, “A Simple Statistical Cache Sharing Model for Multicores,” in Proc. Swedish Workshop on Multi-Core Computing (MCC), Nov. 2011, pp. 31–36. Link PDF
  21. A. Sandberg, D. Eklöv, and E. Hagersten, “A Software Technique for Reducing Cache Pollution,” in Proc. Swedish Workshop on Multi-Core Computing (MCC), Nov. 2010, pp. 59–62. Link PDF
  22. A. Sandberg, D. Eklöv, and E. Hagersten, “Reducing Cache Pollution Through Detection and Elimination of Non-Temporal Memory Accesses,” in Proc. High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2010. doi: 10.1109/SC.2010.44. PDF
  23. A. Sandberg and S. Kaxiras, “Efficient Detection of Communication in Multi-Cores,” in Proc. Swedish Workshop on Multi-Core Computing (MCC), Nov. 2009, pp. 119–121. Link PDF

Patents

US 18/003,841 *
INTEGRITY TREE FOR MEMORY SECURITY
Andreas Lars Sandberg, Roberto Avanzi
US 17/225,674 *
MESSAGE PASSING CIRCUITRY AND METHOD
Jonathan Curtis Beard, Curtis Glenn Dunham, Andreas Lars Sandberg, Roxana Rusitoru
US 17/756,877 *
AN APPARATUS AND METHOD OF CONTROLLING ACCESS TO DATA STORED IN A NON-TRUSTED MEMORY
Hector Montaner Mas, Andreas Lars Sandberg, Roberto Avanzi
US 16/925,723 *
MEMORY PROTECTION USING CACHED PARTIAL HASH VALUES
Roberto Avanzi, Andreas Lars Sandberg, Michael Andrew Campbell, Matthias Lothar Boettcher, Prakash S. Ramrakhyani
APPARATUS AND METHOD
Ilias Vougioukas, Nikos Nikoleris, Andreas Lars Sandberg, Stephan Diestelhorst
ADDRESS DECRYPTION FOR MEMORY STORAGE
Andreas Lars Sandberg, Derek Del Miller
APPARATUS AND METHOD FOR MAINTAINING A COUNTER VALUE
Andreas Lars Sandberg, Matthias Lothar Boettcher
US 17/593,319 *
PAGE TABLE STRUCTURE
Andreas Lars Sandberg, Stephan Diestelhorst
RE-ENCRYPTION FOLLOWING AN OTP UPDATE EVENT
Andreas Lars Sandberg, Matthias Lothar Boettcher, Prakash S. Ramrakhyani
SYSTEM, METHOD AND APPARATUS FOR SECURE FUNCTIONS AND CACHE LINE DATA
Andreas Lars Sandberg, Prakash S. Ramrakhyani
SYSTEM, METHOD AND APPARATUS FOR SECURE FUNCTIONS AND CACHE LINE DATA
Andreas Lars Sandberg, Prakash S. Ramrakhyani
CACHE CONTROL IN PRESENCE OF SPECULATIVE READ OPERATIONS
Andreas Lars Sandberg, Stephan Diestelhorst, Nikos Nikoleris, Ian Michael Caulfield, Peter Richard Greenhalgh, Frederic Claude Marie Piry, Albin Pierrick Tonnerre
MEMORY ADDRESS TRANSLATION
Andreas Lars Sandberg, Nikos Nikoleris, Prakash S. Ramrakhyani
DATA STORAGE FOR MULTIPLE DATA TYPES
Prakash S. Ramrakhyani, Andreas Lars Sandberg, Nikos Nikoleris, Stephan Diestelhorst
PERFORMING MAINTENANCE OPERATIONS
Andreas Lars Sandberg, Nikos Nikoleris, Prakash S. Ramrakhyani, Stephan Diestelhorst
DELAY MASKING ACTION FOR MEMORY ACCESS REQUESTS
Radhika Sanjeev Jagtap, Nikos Nikoleris, Andreas Lars Sandberg
METHODS AND APPARATUS OF CACHE ACCESS TO A DATA ARRAY WITH LOCALITY-DEPENDENT LATENCY CHARACTERISTICS
Radhika Sanjeev Jagtap, Nikos Nikoleris, Andreas Lars Sandberg, Stephan Diestelhorst
PARALLEL PAGE TABLE ENTRY ACCESS WHEN PERFORMING ADDRESS TRANSLATIONS
Geoffrey Wyman Blake, Prakash S. Ramrakhyani, Andreas Lars Sandberg
TAGE BRANCH PREDICTOR WITH PERCEPTRON PREDICTOR AS FALLBACK PREDICTOR
Ilias Vougioukas, Stephan Diestelhorst, Andreas Lars Sandberg, Nikos Nikoleris
SAVING AND RESTORING BRANCH PREDICTION STATE
Ilias Vougioukas, Andreas Lars Sandberg, Stephan Diestelhorst, Matthew James Horsnell
APPARATUS AND METHOD OF HANDLING CACHING OF PERSISTENT DATA
Wei Wang, Stephan Diestelhorst, Wendy Arnott Elsasser, Andreas Lars Sandberg, Nikos Nikoleris
CACHE SECTOR USAGE PREDICTION
Nikos Nikoleris, Andreas Lars Sandberg, Jonas Svedas, Stephan Diestelhorst
A CACHE APPARATUS AND METHOD THAT FACILITATES A REDUCTION IN ENERGY CONSUMPTION THROUGH USE OF FIRST AND SECOND DATA ARRAYS
Ricardo Daniel Queiros Alves, Nikos Nikoleris, Shidhartha Das, Andreas Lars Sandberg
MEMORY ADDRESS TRANSLATION USING STORED KEY ENTRIES
Nikos Nikoleris, Andreas Lars Sandberg, Prakash S. Ramrakhyani, Stephan Diestelhorst
APPARATUS AND METHOD FOR TRANSFERRING DATA BETWEEN ADDRESS RANGES IN MEMORY
Andreas Lars Sandberg, Nikos Nikoleris, David Hennah Mansell
WEAR LEVELLING IN NON-VOLATILE MEMORIES
Andreas Lars Sandberg, Irenéus Johannes de Jong, Andreas Hansson